ALY

User Guide

  • Installation
    • Requirements
    • Installation Methods
      • From PyPI (Recommended)
      • From Source
      • Verify Installation
    • Environment Setup
      • Tool Paths
    • Project Structure
    • Next Steps
  • Quickstart
    • Create a New Project
      • Project Structure
    • Create RTL Module
    • Create Testbench
    • Run Simulation
    • Lint the Design
    • Synthesize
    • Workflow Diagram
    • Next Steps
  • Core Concepts
    • Project Structure
    • Manifest System
      • Manifest Types
    • RTL Modules
      • Module Definition
      • Module Hierarchy
      • File Resolution
    • Testbenches
      • Dependency Types
    • Firmware Builds
      • Build Pipeline
    • IP Management
      • IP Types
    • Build System
      • Backend Architecture
    • Next Steps

Configuration

  • Configuration
    • Configuration Files
    • Configuration Structure
    • Project Information
    • Feature Flags
    • Path Configuration
    • Default Tools
    • Simulation Configuration
      • Tool Options Reference
    • Synthesis Configuration (still under development to be used for synth commands)
      • Synthesis Target Options
    • Lint Configuration
    • Constraints Configuration (Under development)
    • FPGA Configuration (Under development to be used with the program/synth command)
    • Toolchain Configuration
    • Complete Example
    • Next Steps
  • Manifest System
    • Overview
    • RTL Manifest
      • Schema
      • Complete Example
      • Module Class Diagram
    • Testbench Manifest
      • Schema
      • Complete Example
      • Testbench Class Diagram
    • Firmware Manifest
      • Schema
      • Complete Example
      • Firmware Class Diagram
    • IP Manifest
      • Schema
      • Complete Example
      • IP with Nested Manifests
      • IP Class Diagram
    • Validation
    • File Resolution
    • Next Steps
  • Template System
    • Overview
    • Template Directory Structure
    • The template.yaml File
      • Basic Structure
      • Variables Section
      • Structure Section
      • Files Section
        • Glob Patterns in Files
        • Directory Copy Shorthand
        • Conditional File Creation (when:)
      • Hooks Section
      • Template Inheritance
    • Jinja2 Templating
      • Variable Substitution
      • Conditional Content
      • Loops
      • Filters
      • Comments
    • Complete Example
      • template.yaml
      • Template File (rtl/top.sv.j2)
      • Usage
    • Fallback Without Jinja2
    • API Reference
      • TemplateLoader Class
    • Available Templates
  • Constraints (Under Development)
    • Overview
    • Configuration
    • XDC Constraints (Vivado)
      • Pin Assignments
      • Clock Constraints
      • Timing Constraints
      • Clock Domain Crossing
    • PCF Constraints (Yosys/nextpnr)
    • SDC Constraints
    • CLI Commands
      • List Constraints
      • Generate Template
      • Validate Constraints
    • I/O Standards
    • Board Files
    • Template Variables
    • Best Practices
    • Next Steps

Workflows

  • Simulation
    • Overview
    • Basic Usage
    • Simulation Flow
    • Tool Configuration
      • XSim (Xilinx)
      • Verilator
      • QuestaSim
    • Waveform Viewing
    • Test Suites
    • Plusargs
    • Timeouts
    • Show Logs
    • Build Directory
    • Backend Comparison
    • Troubleshooting
      • Common Issues
    • Next Steps
  • Synthesis (Under Development for Enhanced Features)
    • Overview
    • Basic Usage
    • Synthesis Flow
    • Target Configuration
    • Vivado Synthesis
      • Tool Configuration
      • Vivado Options
    • Yosys Synthesis
      • Tool Configuration
      • Technology Targets
    • ASIC Synthesis
    • Constraints
      • XDC (Vivado)
      • PCF (Yosys/nextpnr)
    • Reports
    • Build Artifacts
    • Multi-Clock Designs
    • Debug Cores
    • Troubleshooting
      • Common Issues
    • Next Steps
  • Linting
    • Overview
    • Basic Usage
    • Lint Flow
    • Configuration
    • Lint Rules (Under Development)
      • Verilator Rules
      • Rule Categories
    • Waivers
      • Inline Waivers
    • Output
    • Severity Levels
    • CI Integration (Under Development)
      • GitHub Actions
      • Pre-commit Hook
    • Common Patterns
      • Avoiding Warnings
    • Troubleshooting
      • Common Issues
    • Next Steps
  • IP Management (Under Development for Enhanced Features)
    • Overview
    • IP Directory Structure
    • Creating IP
      • Basic IP Manifest
      • Vendor IP
      • Complex IP with Nested Manifests
    • CLI Commands
      • List IP
      • Show IP Details
    • Using IP in Projects
      • Reference in RTL Manifest
      • Reference in Testbench
    • IP Discovery
    • IP with Internal Structure
    • Binary IP
    • IP Parameters
    • IP Interfaces
    • Best Practices
    • Next Steps

Reference

  • Command Reference
    • Command Overview
    • Global Options
    • init
    • sim
    • synth
    • lint
    • firmware
    • program (still under development)
    • config
    • rtl
    • ip
    • constraints
    • Exit Codes
    • Utility Commands
    • Next Steps
  • API Reference
    • Overview
    • Configuration API
      • ProjectConfig
        • ProjectConfig
    • Model Classes
      • RTLManifest
        • aly.config.models.RTLManifest
      • RTLModule
        • aly.config.models.RTLModule
      • TestbenchManifest
        • aly.config.models.TestbenchManifest
      • Testbench
        • aly.config.models.Testbench
      • FirmwareManifest
        • aly.config.models.FirmwareManifest
      • IPManifest
        • aly.config.models.IPManifest
    • Backend API
      • SimulatorBackend
        • aly.backends.SimulatorBackend
      • SynthBackend
        • aly.backends.SynthBackend
    • Utility Functions
      • Logging
        • get_logger()
        • setup_logging()
      • Configuration Utilities
        • find_project_root()
      • Template System
        • TemplateLoader
    • Usage Examples
      • Loading a Project
      • Running Simulation
      • Programmatic Synthesis
    • Next Steps
  • Architecture
    • System Overview
    • Module Structure
    • Configuration System
      • Configuration Class Hierarchy
      • Unit Registry System
        • Unit Types
        • Discovery Process
      • Manifest Validation
    • Backend System
      • Synthesis Backend Architecture
    • Command Processing
      • Error Handling
    • Dependency Resolution
      • Resolution Algorithm
    • File Organization
    • Design Principles
    • Extension Points
    • Next Steps
  • Examples
    • Simple Counter Project
      • Project Structure
      • Configuration
      • RTL Manifest
      • RTL Code
      • Testbench
      • Commands
    • RISC-V SoC Project
      • Project Structure
      • Configuration
      • RTL Manifest
      • Firmware Manifest
      • Testbench
      • Commands
    • Multi-Target Project
    • IP Reuse Example
      • Create IP
      • Use IP
    • Waveform Debugging Example
    • Next Steps

Project

  • Contributing
    • Getting Started
      • Development Setup
      • Project Structure
    • Development Workflow
      • Creating a Branch
      • Making Changes
      • Submitting Changes
    • Code Style
      • Python Style
      • Commit Messages
    • Testing
      • Running Tests
      • Writing Tests
    • Documentation
      • Building Documentation
      • Writing Documentation
    • Adding New Features
      • Adding a Simulator Backend
      • Adding a CLI Command
    • Release Process
      • Version Bumping
    • Getting Help
    • License
  • License
    • Apache License 2.0
    • What This Means
    • Third-Party Licenses
    • Contact
ALY
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