Simulation

This guide covers simulation workflows and supported tools.

Overview

ALY supports multiple simulation backends with a unified interface.

Figure 16 Supported Simulators

Basic Usage

Run simulation with:

# Simulate with default tool
aly sim --top tb_counter

# Specify simulator
aly sim --top tb_counter --tool verilator

# Enable waveforms
aly sim --top tb_counter --waves

Simulation Flow

Figure 17 Simulation Execution Flow

Tool Configuration

Configure simulators in .aly/config.yaml:

XSim (Xilinx)

simulation:
  tools:
    xsim:
      bin: xsim
      vlog: xvlog
      xelab: xelab
      compile_opts:
        - -sv
        - -d SIMULATION
        - -i include
      elab_opts:
        - -debug typical
        - -relax
      run_opts:
        - -runall
      gui_opts:
        - -gui

Verilator

simulation:
  tools:
    verilator:
      bin: verilator
      args:
        - --binary
        - --trace
        - -Wall
        - -Wno-fatal
        - --timing
        - -j 4

QuestaSim

simulation:
  tools:
    questa:
      bin: vsim
      vlog: vlog
      vsim: vsim
      compile_opts:
        - -sv
        - +define+SIMULATION
      run_opts:
        - -c
        - -do "run -all; quit"
      gui_opts:
        - -do "add wave -r /*; run -all"

Waveform Viewing

Enable waveforms with --waves:

aly sim --top tb_cpu --waves

Each simulator produces different formats:

Simulator	Format	Viewer
XSim	.wdb / .vcd	Vivado waveform viewer
Verilator	.vcd / .fst	GTKWave
QuestaSim	.wlf / .vcd	QuestaSim GUI

Open waveforms in GUI:

# Open with simulator GUI
aly sim --top tb_cpu --waves --gui

# Use GTKWave for .vcd waveforms
aly sim --top tb_cpu --waves --gtkwave

Test Suites

Group related testbenches into suites:

# tb/manifest.yaml
test_suites:
  - name: unit_tests
    testbenches:
      - tb_alu
      - tb_regfile
      - tb_decoder
    parallel: 2

  - name: integration
    testbenches:
      - tb_cpu
      - tb_memory
    parallel: 8

  - name: regression
    testbenches:
      - tb_alu
      - tb_cpu
      - tb_soc
    parallel: 8
    timeout: 300

Run suites:

# Run specific suite
aly sim --suite unit_tests

# Run all tests (regression mode)
aly sim --regress

# Run specific test by name
aly sim --test tb_alu

# Run tests in parallel
aly sim --suite regression -j 4

# Stop on first failure
aly sim --regress --stop-on-fail

# List available tests
aly sim --list

# List test suites
aly sim --list-suites

# List tests by tag
aly sim --list-tags

Plusargs

Pass runtime arguments:

aly sim --top tb_cpu \
    --plusargs FIRMWARE=boot.hex \
    --plusargs TIMEOUT=1000000 \
    --plusargs VERBOSE=1

Access in testbench:

string firmware_file;
initial begin
    if ($value$plusargs("FIRMWARE=%s", firmware_file)) begin
        $display("Loading firmware: %s", firmware_file);
        $readmemh(firmware_file, memory.mem);
    end
end

Timeouts

Set simulation timeout (in seconds):

# Command line (timeout in seconds)
aly sim --top tb_cpu --timeout 300

In manifest:

testbenches:
  - name: tb_cpu
    timeout: 300  # seconds

Show Logs

Display simulation logs in real-time:

aly sim --top tb_cpu --show-log

Build Directory

Simulation artifacts are stored in the build directory:

build/
+-- sim/
    +-- xsim/
    |   +-- work/              # Compiled library
    |   +-- tb_cpu.wdb         # Waveforms
    +-- verilator/
    |   +-- obj_dir/           # Object files
    |   +-- Vtb_cpu            # Executable
    |   +-- trace.vcd          # Waveforms
    +-- questa/
        +-- work/              # Library
        +-- vsim.wlf           # Waveforms

Backend Comparison

Feature	XSim	Verilator	QuestaSim	Icarus
Speed	Medium	Fast	Medium	Slow
SV Support	Full	Partial	Full	Limited
Waveforms	.wdb/.vcd	.vcd/.fst	.wlf/.vcd	.vcd
UVM	Yes	No	Yes	No
License	Xilinx	Open Source	Commercial	Open Source

Troubleshooting

Common Issues

Compilation errors:

Check the simulation log for details:

aly sim --top tb_cpu --show-log

Timeout:

# Increase timeout (in seconds)
aly sim --top tb_cpu --timeout 3600

Missing dependencies:

Check manifest dependencies:

testbenches:
  - name: tb_cpu
    dependencies:
     - name: cpu_core # Ensure this module exists
       type: rtl
     - name: alu
       type: rtl

Next Steps

• Synthesis (Under Development for Enhanced Features) - Synthesis workflows

• Command Reference - Full CLI reference

• Manifest System - Testbench manifest details