ALY - Advanced Logic Yieldflow

ALY is a comprehensive HDL/FPGA development tool that streamlines the entire hardware design workflow from RTL development through simulation, synthesis, and FPGA programming.

digraph overview { rankdir=LR; node [shape=box, style="rounded,filled", fontname="sans-serif"]; edge [fontname="sans-serif"]; RTL [label="RTL Design", fillcolor="#e1f5fe"]; Sim [label="Simulation", fillcolor="#fff3e0"]; Synth [label="Synthesis", fillcolor="#f3e5f5"]; FPGA [label="FPGA", fillcolor="#e8f5e9"]; RTL -> Sim -> Synth -> FPGA; }

Key Features

  • Manifest-Based Project Management: YAML manifests for RTL, testbench, firmware, and IP components

  • Multi-Tool Support: Works with Vivado, Yosys, Verilator, QuestaSim, and more

  • Unified CLI: Single command-line interface for all development tasks

  • Template System: Quick project scaffolding with customizable templates

  • Hierarchical Configuration: Project-wide settings with per-component overrides

Getting Started

# Install ALY
pip install aly-tool

# Initialize a new project
aly init my_project --template basic

# Run simulation
aly sim --top my_testbench

# Synthesize design
aly synth --module my_design

Indices and tables